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December 2004
(R)
AS7C331MFT32A AS7C331MFT36A
3.3V 1M x 32/36 Flow-through synchronous SRAM
Features
* * * * * * * Organization: 1,048,576 words x 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write * * * * * * Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
Logic block diagram
LBO CLK ADV ADSC ADSP A[19:0] 20 CLK CE CLR Q0 Burst logic Q1
2 2
D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Q
1M x 32/36 Memory array
20
18
20 32/36 32/36
GWE BWE BWd
BWc
BWb
BWa CE0 CE1 CE2
4
OE Output registers CLK
Input registers CLK
ZZ
Power down
D Enable Q delay register CLK 32/36 DQ[a:d]
OE
Selection guide
Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
-75 8.5 7.5 325 140 90
-85 10 8.5 300 130 90
-10 12 10 275 130 90
Units ns ns mA mA mA
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Copyright (c) Alliance Semiconductor. All rights reserved.
AS7C331MFT32A AS7C331MFT36A
(R)
32 Mb Synchronous SRAM products list1,2
Org 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 Part Number AS7C332MPFS18A AS7C331MPFS32A AS7C331MPFS36A AS7C332MPFD18A AS7C331MPFD32A AS7C331MPFD36A AS7C332MFT18A AS7C331MFT32A AS7C331MFT36A AS7C332MNTD18A AS7C331MNTD32A AS7C331MNTD36A AS7C332MNTF18A AS7C331MNTF32A AS7C331MNTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
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AS7C331MFT32A AS7C331MFT36A
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Pin assignment 100-pin TQFP - top view
A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
TQFP 14 x 20mm
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
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LBO A A A A A1 A0 NC A VSS VDD A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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AS7C331MFT32A AS7C331MFT36A
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Functional description
The AS7C331MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x 32 or 36 bits. Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/ 36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). * Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C331MFT32A and AS7C331MFT36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
Parameter Input capacitance I/O capacitance
*Guaranteed not tested
Symbol CIN
*
Test conditions VIN = 0V VOUT = 0V
Min -
Max 5 7
Unit pF pF
CI/O*
TQFP thermal resistance
Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1
1 This parameter is sampled
Conditions 1-layer Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 4-layer
Symbol JA JA JC
Typical 40 22 8
Units C/W C/W C/W
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AS7C331MFT32A AS7C331MFT36A
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Signal descriptions
Pin CLK A,A0,A1 DQ[a,b,c,d] CE0 CE1, CE2 ADSP ADSC ADV GWE BWE BW[a,b,c,d] OE LBO ZZ NC I/O I I I/O I I I I I I I I I I I Properties CLOCK SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ASYNC STATIC ASYNC -
Description
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and when OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the "Synchronous truth table" for more information. Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted low to load a new address or to enter standby mode. Address strobe controller. Asserted low to load a new address or to enter standby mode. Advance. Asserted low to continue burst read/write. Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write enable. Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode. Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
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AS7C331MFT32A AS7C331MFT36A
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Write enable truth table (per byte)
Function
Write All Bytes Write Byte a Write Byte c and d Read
GWE L H H H H H
BWE X L L L H L
BWa X L L H X H
BWb X L H H X H
BWc X L H L X H
BWd X L H L X H
Key: X = don't care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation Snooze mode Read Write Deselected ZZ H L L L L OE X L H X X I/O Status High-Z Dout High-Z Din, High-Z High-Z
Notes: 1. X means "Don't Care" 2. ZZ pin is pulled down internally 3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Snooze mode means power down state of which stand-by current does not depend on cycle times 5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address (LBO = 1) A1 A0
1 Address 2nd Address 3 Address 4th Address
rd st
Linear burst address (LBO = 0) A1 A0 11 10 01 00
1 Address 2nd Address 3 Address 4th Address
rd st
A1 A0 01 00 11 10
A1 A0 10 11 00 01
A1 A0 00 01 10 11
A1 A0 01 10 11 10
A1 A0 10 11 00 01
A1 A0 11 00 01 10
00 01 10 11
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AS7C331MFT32A AS7C331MFT36A
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Synchronous truth table[4]
CE01 CE1 CE2 ADSP ADSC ADV WRITE[2] OE Address accessed CLK Operation DQ
H L L L L L L L L X X X X H H H H L X H X H
X L L X X H H H H X X X X X X X X H X X X X
X X X H H L L L L X X X X X X X X L X X X X
X L H L H L L H H H H H H X X X X H H X H X
L X L X L X X L L H H H H H H H H L H H H H
X X X X X X X X X L L H H L L H H X L L H H
X X X X X X X H H H H H H H H H H L L L L L
X X X X X L H L H L H L H L H L H X X X X X
NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current
L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H
Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D3 D D D D
1 X = don't care, L = low, H = high 2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information. 3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
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AS7C331MFT32A AS7C331MFT36A
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Absolute maximum ratings
Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation Short circuit output current Storage temperature Temperature under bias Symbol VDD, VDDQ VIN VIN Pd IOUT Tstg Tbias Min -0.5 -0.5 -0.5 - - -65 -65 Max +4.6 VDD + 0.5 VDDQ + 0.5 1.8 20 +150 +135 Unit V V V W mA
o o
C C
Stresses greater than those listed under "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 3.135 0 Nominal 3.3 3.3 0 Max 3.465 3.465 0 Unit V V V
Recommended operating conditions at 2.5V I/O
Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 2.375 0 Nominal 3.3 2.5 0 Max 3.465 2.625 0 Unit V V V
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AS7C331MFT32A AS7C331MFT36A
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DC electrical characteristics for 3.3V I/O operation
Parameter Input leakage current Sym |ILI| |ILO| VIH VIL VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = -4 mA, VDDQ = 3.135V IOL = 8 mA, VDDQ = 3.465V Min -2 -2 2* 2* -0.3** -0.5** 2.4 - Max 2 2 VDD+0.3 VDDQ+0.3 0.8 0.8 - 0.4 Unit A A V
Output leakage current Input high (logic 1) voltage
Input low (logic 0) voltage Output high voltage Output low voltage
V V V
DC electrical characteristics for 2.5V I/O operation
Parameter Input leakage current Sym |ILI| |ILO| VIH VIL VOH VOL Conditions VDD = Max, 0V < VIN < VDD OE VIH, VDD = Max, 0V < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = -4 mA, VDDQ = 2.375V IOL = 8 mA, VDDQ = 2.625V Min -2 -2 1.7* 1.7* -0.3** -0.3** 1.7 - Max 2 2 VDD+0.3 VDDQ+0.3 0.7 0.7 - 0.7 Unit A A V V V V V V
Output leakage current Input high (logic 1) voltage
Input low (logic 0) voltage Output high voltage Output low voltage
LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = 10 A. *V max < VDD +1.5V for pulse width less than 0.2 X t IH CYC
**V IL min
= -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter Operating power supply current1 Sym ICC ISB Standby power supply current ISB1 ISB2 Conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN 0.2V or > VDD - 0.2V, Deselected, f = fMax, ZZ < VIL Deselected, f = 0, ZZ < 0.2V, all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V, all VIN VIL or VIH -75 325 140 90 80 -85 300 130 90 80 -10 275 130 90 80 mA Unit mA
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
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AS7C331MFT32A AS7C331MFT36A
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Timing characteristics over operating range
-75 Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable high to output high Z Clock high to output high Z Output enable high to invalid output Clock high pulse width Clock low pulse width Address setup to clock high Data setup to clock high Write setup to clock high Chip select setup to clock high Address hold from clock high Data hold from clock high Write hold from clock high Chip select hold from clock high ADV setup to clock high ADSP setup to clock high ADSC setup to clock high ADV hold from clock high ADSP hold from clock high ADSC hold from clock high
1 See "Notes" on page 16.
-85 Min 10 - - 2.5 2.5 0 - - 0 3.0 3.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 2.0 2.0 0.5 0.5 0.5 Max - 8.5 4.0 - - - 4.0 5.0 - - - - - - - - - - - - - - - - - Min 12 - - 2.5 2.5 0 - - 0 3.0 3.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 2.0 2.0 0.5 0.5 0.5 - 7.5 3.5 - - - 3.5 4.0 - - - - - - - - - - - - - - - - -
-10 Max - 10 4.0 - - - 4.0 5.0 - - - - - - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 2,3,4 2 2,3,4 2,3,4 2,3,4 Notes1
Sym tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH
Min 8.5 - - 2.5 2.5 0 0 2.5 2.5 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 2.0 2.0 2.0 0.5 0.5 0.5
Max
Snooze Mode Electrical Characteristics
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current
ZZ > VIH
ISB2 tPDS tPUS tZZI tRZZI
80 2 2 2 0
mA cycle cycle cycle
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AS7C331MFT32A AS7C331MFT36A
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Key to switching waveforms
Rising input Falling input don't care Undefined
Timing waveform of read cycle
tCH CLK tADSPS ADSP tADSCS ADSC tAS Address A1 tWS GWE, BWE tCSS CE0, CE2 tCSH tAH A2 tWH LOAD NEW ADDRESS A3 tADSCH tADSPH tCYC tCL
CE1 tADVS ADV ADV inserts wait states OE tADVH
tOE tLZOE Dout
Q(A1)
tHZOE
tOH
Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11)
tCD
Read Q(A1) Suspend Read Q(A1) Read Q(A2)
tHZC
DSEL
Burst Burst Read Suspend Burst Burst Burst Burst Read Read Q(A3) Read Read Read Read Read Q(A 2Y01) Q(A 2Y10) Q(A 2Y10) Q(A 2Y11) Q(A 3Y01) Q(A 3Y10) Q(A 3Y11)
Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. BW[a:d] is don't care.
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AS7C331MFT32A AS7C331MFT36A
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Timing waveform of write cycle
tCYC tCL
tCH CLK tADSPS tADSPH ADSP
tADSCS tADSCH ADSC tAS tAH Address A1 A2 ADSC LOADS NEW ADDRESS A3 tWS tWH
BW[a:d]
BWE tCSS tCSH
CE0, CE2
CE1 ADV SUSPENDS BURST ADV tADVS tADVH
OE tDS Din
Read Q(A1)
D(A1) D(A2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) D(A3) D(A3Y01)
tDH
D(A3Y10)
Suspend Write D(A1)
Read Q(A2)
Suspend Write D(A 2)
ADV Suspend ADV ADV Burst Write Burst Burst Write D(A 2Y01) Write Write D(A 2Y01) D(A 2Y10) D(A 2Y11)
Write D(A 3)
Burst Write D(A 3Y01)
ADV Burst Write D(A 3Y10)
Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low.
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AS7C331MFT32A AS7C331MFT36A
(R)
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCH CLK tADSPS tADSPH ADSP tAS tAH Address A1 A2 A3 tWS tWH tCYC tCL
BWE BW[a:d] CE0, CE2
CE1 tADVS tADVH ADV
OE tDS tDH Din tCD Dout tLZC tHZOE
Q(A1) D(A2)
tOE tLZOE
Q(A3)
tOH
Q(A3Y01) Q(A3Y10) Q(A3Y11)
Read Q(A1)
Suspend Read Q(A1)
Read Q(A2)
Suspend Write D(A 2)
Read Q(A3)
ADV Burst Read Q(A 3Y01)
ADV Burst Read Q(A 3Y10)
ADV Burst Read Q(A 3Y11)
Suspend Read Q(A 3Y11)
Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low.
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AS7C331MFT32A AS7C331MFT36A
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCH CLK tADSCS ADSC tADSCH tCYC tCL
tAS ADDRESS
A1 A2 A3 A4 A5 A6 A7 A8
tAH
A9 A10
BWE BW[a:d] tCSS CE0,CE2 tCSH
tWS
tWH
CE1
OE tOE tLZOE Dout
Q(A1) Q(A2) Q(A3)
tHZOE
Q(A4)
tCD
tOH
Q(A9) Q(A10)
tDS Din
D(A5) D(A6)
tDH
D(A7) D(A8)
READ Q(A1)
READ Q(A2)
READ Q(A3)
READ Q(A4)
WRITE WRITE WRITE WRITE D(A6) D(A7) D(A8) D(A5)
READ Q(A9)
READ Q(A10)
Note: ADV is don't care here.
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AS7C331MFT32A AS7C331MFT36A
(R)
Timing waveform of power down cycle
tCH CLK tADSPS ADSP tADSPS tCYC tCL
ADSC
ADDRESS BWE BW[a:d] tCSS CE0,CE2
A1
A2 tWS tWH
tCSH
CE1
ADV OE tOE Din tLZOE tHZOE tHZC Dout
Q(A1) Q(A2)
tPDS ZZ
ZZ Setup Cycle
tPUS
ZZ Recovery Cycle Normal Operation Mode
Q(A2(Y01))
tZZI Isupply
tRZZI ISB2
Sleep State
READ Q(A1)
READ Q(A1Y01)
READ Q(A2)
READ Q(A2Y01)
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AS7C331MFT32A AS7C331MFT36A
(R)
AC test conditions
* Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B. * Input pulse level: GND to 3V. See Figure A. * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. * Input and output timing reference levels: 1.5V. +3.0V DOUT Z0 = 50 50 VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O DOUT 353/1538 Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319/1667 5 pF* GND *including scope and jig capacitance
90%
10% GND
90% 10%
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1 2 3 4 5 6 7 8 For test conditions, see "AC test conditions", Figures A, B, and C. This parameter is measured with output load condition in Figure C. This parameter is sampled but not 100% tested. tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage. tCH is measured as high if above VIH, and tCL is measured as low if below VIL. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. Write refers to GWE, BWE, and BW[a:d]. Chip select refers to CE0, CE1, and CE2.
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AS7C331MFT32A AS7C331MFT36A
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Package dimensions 100-pin quad flat pack (TQFP)
TQFP Min Max
A1 A2 b c D E e Hd He L L1 0.05 1.35 0.22 0.09 13.90 19.90 15.85 21.80 0.45 0 0.15 1.45 0.38 0.20 14.10 20.10 16.15 22.20 0.75 7
Hd D b e
0.65 nominal
He E
1.00 nominal
Dimensions in millimeters
c L1 L A1 A2
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AS7C331MFT32A AS7C331MFT36A
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Ordering information
Package & Width TQFP x32 TQFP x36 -75 AS7C331MFT32A-75TQC AS7C331MFT32A-75TQI AS7C331MFT36A-75TQC AS7C331MFT36A-75TQI -85 AS7C331MFT32A-85TQC AS7C331MFT32A-85TQI AS7C331MFT36A-85TQC AS7C331MFT36A-85TQI -10 AS7C331MFT32A-10TQC AS7C331MFT32A-10TQI AS7C331MFT36A-10TQC AS7C331MFT36A-10TQI
Note: Add suffix `N' to the above part number for Lead Free Parts (Ex. AS7C331MFT32A-75TQCN)
Part numbering guide
AS7C 1 33 2 1M 3 FT 4 32/36 5 A 6 -XX 7 TQ 8 C/I 9 X 10
1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33 = 3.3V 3.Organization: 1M = 1Meg 4.Flow-through mode 5.Organization: 32 = x 32; 36 = x 36 6.Production version: A = first production version 7.Clock access time: [-75 = 7.5 ns;-85 = 8.5 ns; -10 = 10.0 ns] 8.Package type: TQ = TQFP 9.Operating temperature: C = commercial (0 C to 70 C); I = industrial (-40 C to 85 C) 10. N = Lead free part
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AS7C331MFT32A AS7C331MFT36A
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(R)
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C331MFT32A AS7C331MFT36A Document Version: v 1.3
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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